The present invention generally relates to fabrication methods and resulting structures for semiconductor devices, and more specifically, to the removal of epitaxy defect regions (or nodules) from transistor features such as dummy gates, hard masks, and spacers.
Traditional metal oxide semiconductor field effect transistor (MOSFET) fabrication techniques include process flows for constructing planar field effect transistors (FETs). A planar FET includes a substrate (also referred to as a silicon slab), a gate formed over the substrate, source and drain regions formed on opposite ends of the gate, and a channel region near the surface of the substrate under the gate. The channel region electrically connects the source region to the drain region while the gate controls the current in the channel. The gate voltage controls whether the path from drain to source is an open circuit (“off”) or a resistive path (“on”).
In recent years, research has been devoted to the development of nonplanar transistor architectures. Some non-planar transistor architectures, such as fin-type field effect transistors (finFETs) and nanosheet field effect transistors (NSFETs), employ semiconductor channels with various replacement metal gate (RMG) and gate-all-around (GAA) technologies to achieve increased device density, greater power efficiency, and some increased performance over lateral devices. In a finFET, for example, a gate runs along the sidewalls and top surface of each semiconductor fin, enabling fuller depletion in the channel region, and reducing short-channel effects due to steeper subthreshold swing (SS) and smaller drain induced barrier lowering (DIBL). Epitaxial growth processes are used to form many of the features (e.g., the source/drain) of these non-planar transistors.